AXI Bus Hardware Accelerator IP for SAR Image Processor Onboard Airborne

Good Fried Panggabean; Josaphat Tetuko Sri  Sumantyo; Chua Ming Yam; Hiroaki Kuze; Pakhrur Razi; Farohaji Kurniawan

doi:10.21535/t8rmbt39

Vol. 7 No. 2 (2019), Research Paper

Vol. 7 No. 2 (2019)

AXI Bus Hardware Accelerator IP for SAR Image Processor Onboard Airborne

Research Paper

Published 2019-07-07

Good Fried Panggabean⁺⁻
Josaphat Tetuko Sri Sumantyo⁺⁻
Chua Ming Yam⁺⁻
Hiroaki Kuze⁺⁻
Pakhrur Razi ⁺⁻
Farohaji Kurniawan⁺⁻

Good Fried Panggabean

Josaphat Microwave Remote Sensing Laboratory, Center for Environmental Remote Sensing, Chiba University

Josaphat Tetuko Sri Sumantyo

Center for Environmental Remote Sensing, Chiba University, 1-33, Yayoi, Inage, Chiba 263-8522, Japan.

Chua Ming Yam

Center for Environmental Remote Sensing, Chiba University, 1-33, Yayoi, Inage, Chiba 263-8522, Japan.

Hiroaki Kuze

Center for Environmental Remote Sensing, Chiba University, 1-33, Yayoi, Inage, Chiba 263-8522, Japan.

Pakhrur Razi

Center for Environmental Remote Sensing, Chiba University, 1-33, Yayoi, Inage, Chiba 263-8522, Japan.

Farohaji Kurniawan

Center for Environmental Remote Sensing, Chiba University, 1-33, Yayoi, Inage, Chiba 263-8522, Japan.

Keywords

SAR image processor
AXI bus hardware accelerator
Airborne SAR
RDA

Abstract

This paper presents how a Synthetic Aperture Radar (SAR) image processor based on AXI Bus Hardware Accelerator (HA) IP was proposed and developed. The SAR image processor is targeted for use in an airborne Circularly Polarized SAR (CP-SAR) system. In the processor, The HA IP was built using software and hardware co-design approach to cater for the high computational requirement in the SAR image formation process. The IP core accelerators are based on Advanced eXtensible Interface (AXI) Bus for its highly configurable. In addition, it is easy to get integrated with another IP core through an on-chip bus and low-cost in implementation. The IP core is co-assisted by MicroBlaze softcore processor in order to accelerate the Range Doppler Algorithm (RDA) processing, which is the most commonly used algorithm for SAR image formation. The proposed SAR image processor was implemented on a Xilinx Artix-7 FPGA AC701 Evaluation Kit using multi-core hardware accelerator and configured to work on raw data with segment size of 8192x8192 pixels. Several optimization techniques such as pipelining and parallelization were applied to the initial design to speed up the processing task and to reduce the resource utilization. The functionality of the implemented SAR image processor is validated by processing a raw dataset from recorded by ALOS PALSAR sensor. The results showed that the proposed SAR imaging processor could process SAR raw data in near real-time.